GAT Subject
Engineering
Computer Science Civil Engineering Chemical Engineering Agricultural Engineering Mechanical Engineering Electronics and Communication
16. | The output 0 and 1 levels for TTL logic family is approximately | |
A. | 0.1 and 5 V | |
B. | 0.6 and 3.5 V | |
C. | 0.9 and 1.75V | |
D. | -1.75 and -0.9 V | |