GAT Subject
Engineering
Computer Science Civil Engineering Chemical Engineering Agricultural Engineering Mechanical Engineering Electronics and Communication
16. | The output 0 and 1 levels for TTL logic family is approximately | ||
A. | 0.1 and 5 V | ||
B. | 0.6 and 3.5 V | ||
C. | 0.9 and 1.75V | ||
D. | -1.75 and -0.9 V | ||
17. | A _____ TTL device can sink up to 16mA and can source up to 400 MA. | ||
A. | Low-power | ||
B. | high-power | ||
C. | Standard | ||
D. | Schottky | ||
18. | Digital design often starts by constructing a _____ table. | ||
A. | Standard | ||
B. | Two-stage | ||
C. | Truth | ||
D. | Two-dinensional | ||
19. | The hexadecimal digits are 0 to 9 and A to _____ | ||
A. | E | ||
B. | F | ||
C. | G | ||
D. | D | ||
20. | The ASCII | ||
A. | is a subset of 8-bit EBCDIC | ||
B. | is used only in Western Countries | ||
C. | is version II of the ASC Standard | ||
D. | has 128 characters, including 32 control characters | ||